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2003 Microchip Technology Inc.

DS39582B-page 129

PIC16F87XA

The ADRESH:ADRESL registers contain the 10-bit

result of the A/D conversion. When the A/D conversion

is complete, the result is loaded into this A/D Result

and the A/D interrupt flag bit ADIF is set. The block

diagram of the A/D module is shown in Figure 11-1.

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as inputs.

To determine sample time, see Section 11.1 “A/D

Acquisition Requirements”. After this acquisition

time has elapsed, the A/D conversion can be started.

To do an A/D Conversion, follow these steps:

Configure the A/D module:

Configure analog pins/voltage reference and

digital I/O (ADCON1)

Select A/D input channel (ADCON0)

Select A/D conversion clock (ADCON0)

Turn on A/D module (ADCON0)

Configure A/D interrupt (if desired):

Clear ADIF bit

Set ADIE bit

Set PEIE bit

Set GIE bit

Wait the required acquisition time.

Start conversion:

Set GO/DONE bit (ADCON0)

Wait for A/D conversion to complete by either:

Polling for the GO/DONE bit to be cleared

(interrupts disabled); OR

Waiting for the A/D interrupt

Read

A/D

Result

pair

(ADRESH:ADRESL), clear bit ADIF if required.

For the next conversion, go to step 1 or step 2

as required. The A/D conversion time per bit is

defined as TAD.

FIGURE 11-1:

A/D BLOCK DIAGRAM

(Input Voltage)

VAIN

VREF+

(Reference

Voltage)

VDD

PCFG3:PCFG0

CHS2:CHS0

RE2/AN7(1)

RE1/AN6(1)

RE0/AN5(1)

RA5/AN4

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

111

110

101

100

011

010

001

000

A/D

Converter

Note

1: Not available on 28-pin devices.

VREF-

(Reference

Voltage)

VSS

PCFG3:PCFG0

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